1. Field of the Invention
The present invention generally relates to electrostatic discharge protection techniques for semiconductor integrated circuitry, and, more specifically, relates to a lateral silicon-controlled rectifier for electrostatic discharge protection.
2. Description of the Prior Art
Electrostatic discharge, ESD hereinafter, is a common phenomenon that occurs during handling of semiconductor integrated circuit ("IC") devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stressing typically can occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely hamper its operation.
However, sub-micron CMOS IC have become increasingly vulnerable to ESD damage due to advanced processes, such as the use of a lightly-doped drain ("LDD") structure and clad silicide diffusions. Therefore, lateral silicon-controlled rectifiers (LSCRs) have been proposed, for example, in U.S. Pat. No. 5,012,317, as ESD protection circuits for facilitating ESD protection. The cross-sectional view of a conventional lateral silicon-controlled rectifier fabricated onto a semiconductor substrate is illustrated in FIG. 1.
As shown in FIG. 1, the silicon-controlled rectifier is fabricated on a P-type silicon substrate 10 in which an N-well region 11 is formed. A P-type doped region 12 and an N-type doped region 13 are formed within the extent of the N-well region 11 and spaced apart from each other, while an N-type doped region 14 and a P-type doped region 15 are formed within the extent of the P-type silicon substrate 10 and spaced apart from each other. The P-type doped region 12 and the N-type doped region 13 are connected together to an IC pad 1. The IC pad 1 is electrically coupled to an internal circuit 2, which is vulnerable to ESD damage and should be protected by the lateral silicon-controlled rectifier. In addition, the N- type doped region 14 and the P-type doped region 15 are connected together to a potential node V.sub.SS, which is generally coupled to grounding potential under normal operation.
Accordingly, the P-type doped region 12, the N-well region 11, and the P-type silicon substrate 10 serve as the emitter, base, and collector, respectively, of a PNP bipolar junction transistor 20; the N-well region 11, the P-type silicon substrate 10, and the N-type doped region 14 serve as the collector, base, and emitter, respectively, of an NPN bipolar junction transistor 21. Referring to FIG. 2, the equivalent circuit diagram of the conventional lateral silicon-controlled rectifier shown in FIG. 1 is schematically depicted. In FIG. 2, resistors 22 and 23 stand for the spreading resistance of the N-well region 11 and the P-type silicon substrate 10, respectively.
When ESD stress occurs at the IC pad 1, the P/N junction between the N-well region 11 and the P-type silicon substrate 10 sustains breakdown so as to forward bias the P/N junction of the P-type silicon substrate 10 and the N-type doped region 14. Therefore, the lateral silicon-controlled rectifier composed of the PNP transistor 20, NPN transistor 21 and the resistors 22 and 23 is triggered to conduct the resulting ESD current and thus bypass the ESD stress so as to protect the internal circuit 2 from ESD damage.
As mentioned above, triggering the conventional lateral silicon-controlled rectifier to turn on and thus bypass the ESD stress occurring at the IC pad 1 heavily relies on the junction breakdown between the N-well region 11 and the P-type silicon substrate 10. However, both N-well region 11 and the P-type silicon substrate 10 have doping concentrations so low that the trigger voltage of the lateral silicon-controlled rectifier is roughly 30V or more. For example, with CMOS fabrication technology of 0.6.about.0.8 .mu.m, gate oxides of about 150.about.200 .ANG. in thickness, deployed in the internal circuit 2, may be damaged at voltages lower than the trigger voltage of the conventional lateral silicon-controlled rectifier.
For the foregoing reason, there is a need for a lateral silicon-controlled rectifier provided with a lower trigger voltage so as protect the internal circuit from ESD damage.